dataavailable / waitrequest questions

--- Quote Start ---

originally posted by siva prasad motamarri@Oct 12 2006, 09:54 PM

hi andrew,

i am beginner with nios.. i have to use the old code provided by our customer for the new project. there i am seeing 'wait_writerequest' output port in port map of block-ram module. actually nios core will update the ram and fpga has to read the ram when required. i am a bit confused with 'wait_writerequest' o/p port.. usually block-ram wont provide this kind of ports.. since you are talking on flow-control component.. i am wondering this particular block-ram access might be related flow controlled ram access.. can you please give some details on flow control component.. and its manual.. i couldn't locate it sopc component list.

thanks,

siva

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=18664)

--- quote end ---

--- Quote End ---

Siva,

Flow control is not a component, just a feature of the Avalon bus. The manual that describes these things is the "Avalon Interface Specification", which you can find here: http://www.altera.com/literature/manual/mnl_avalon_spec.pdf (http://www.altera.com/literature/manual/mnl_avalon_spec.pdf).

I&#39;m sorry I can&#39;t be of any help with RAM components - haven&#39;t ventured into that territory yet - but with the bus spec and the other Altera literature that comes with the NIOS kit you will probably be able to figure out what is going on.

Andrew