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Altera_Forum
Honored Contributor
Honored ContributorData Transfer from FPGA to HPS Via FPGA connected SDRAM (DE1-SoC)
I have not written code to do this yet, but I thought I would describe my plan here in the hope that any experts present might give me a heads up on any possible problems. I have a NIOS gatheri...
Altera_ForumHonored Contributor
Honored ContributorThis should be handled by the memory controller which should arbit the ports to it to enforce the correct functionality...
So from the view of the NIOS a read/write is atomic. If you have a bursting Core with e.g. a 128-bit Avalon-MM Interface with 32 bursts and the controller is able to handle that, than a burst of 32 128-bit words should be seen as atomic... And the 16-bit Interface is "only" the physical view of the RAM-Interface...
