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Altera_Forum
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11 years ago

Data Transfer from FPGA to HPS Via FPGA connected SDRAM (DE1-SoC)

I have not written code to do this yet, but I thought I would describe my plan here in the hope that any experts present might give me a heads up on any possible problems.

I have a NIOS gathering data and placing it into the FPGA attached (16 bit bus) SDRAM. The HPS monitors and reads data from the SDRAM through the AXI bridge. Provided 32 bit words are written / read atomically I will have no problems. However I am somewhat worried about the SDRAM being attached by a 16 bit interface. I am not familiar with the details but expect that a 32-bit transfer from the NIOS to the SDRAM results in two (!) writes to the SDRAM. What if the HPS tries to read exactly in the middle of this write by the NIOS? Is it possible I could read half the old word and half of the new one? Or is the bus clever enough to make sure this does not happen?

Many thanks

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    This should be handled by the memory controller which should arbit the ports to it to enforce the correct functionality...

    So from the view of the NIOS a read/write is atomic. If you have a bursting Core with e.g. a 128-bit Avalon-MM Interface with 32 bursts and the controller is able to handle that, than a burst of 32 128-bit words should be seen as atomic...

    And the 16-bit Interface is "only" the physical view of the RAM-Interface...
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    OK so If I have understood you correctly the HPS will never read a half written word from the NIOS?