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Why can't you adjust your VHDL code to output and accept 16 bit data. That seems like the simplest approach. Also, since all you are doing is scaling, why wouldn't you do this operation also in VHDL. You are creating a huge bottleneck in your data flow by using the NIOS to scale your data. Floating point operation in software are incredibly slow... Ideally, the NIOS should not be doing data processing, it should just be doing management.
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Thanks Krasner for the reply...
To answer your first question, yes you are right, I did change in the vhdl code so that the input to the NIos is always 16 bits.
data <= to_slv(resize(scale*to_sfixed(in, 0, -11), 9, -6));
Second question, actually there are some processing tasks being done in Nios, I just put *a as an example, sorry for the confusion...
I am still having issue where the value sent from NIos to the fpga is not correct, I tried with iowr, iowr16direct and also using macros without iowr, but still the value sent to the fpga is not correct... I lost direction on which aspect to troubleshoot....sorry, I don't know what else information I should provide here? I updated in the following, I hope you could spend some time have a look, just to give a hint on what I can do, many thanks
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