Data Exchange between FPGA and NIOS2

Hi wangyue2725,

did you solve it?

I am working on the same topic.

I set up a dual port ram block in qsys with the 2nd slave port exported. i wanted to connect this port to a vhdl module. For testing i connected the address and readdata lines.

Since a read happens every clock cycle without explicitly enable;

i thought i could write in C directly to the baseaddress of the dpram and directly read this value from my custom vhdl module.

in order to do so i assigned from the vhdl module the baseaddress to the dpram and read the value, hoping at one point i would see the value written from the c program.

But this approach does not work.

Could you help me with this issue or tell me how you connected your component to the second slave port ?

Cheers

Tim