Forum Discussion
Altera_Forum
Honored Contributor
11 years agoThanks for all your reply!
It Works and finally get this done ! It turns out to be right I use a dual port ram in NIOS2 and connect port s1 to NIOS2 CPU , port s2 is exported to FPGA top level entity. I am now wondering how to read and write to port S2 in fpga. below is my Qsys file and top level entity in FPGA project https://www.alteraforum.com/forum/attachment.php?attachmentid=8833 https://www.alteraforum.com/forum/attachment.php?attachmentid=8834