Data Cache

I'm not too familar with that, however the reason why the cache/no-cache access is set up this way is to allow for fast bypassing. The hardware simply detects this bit and bypasses the cache in hardware (and this is the fastest possible access you can have to non-cache memory).

Wombat also brought up a good point. You really want to locate your addresses near 0x00000000 simply because with any addressing logic comes mux logic. If you map the peripherals all over the place in the address space you may cause not only wasteful LE usage, but poor timing performance. If you want a good optimized mapping use the auto assign base addresses function in SOPC Builder which will modify the addressing in order to make a tightly packed addressing map (with tight address packing some of the multiplexor logic just becomes decoding based off a few msb address bits).

Another recommendation is if you don't require interrupts on some devices, then make it a no connect (NC) and use up the highest priority IRQs first (so instead of 0, 3, 15, 21; use 0, 1, 2, 3 for example).