Cyclone V SPI master releases chip select when TX FIFO runs empty. HOW TO PREVENT???

I did. The SPI clock (at least in my case) was initially low causing the first transfer to fail. So I added sending of one byte without the GPIO CS enable in the driver setup function. From then on the clock is always high prior to a transaction.

I also made a modification of the spi_transfer_one_message function and added it to the spi-dw.c driver. I simply merged the two spi transfers (write and read) into a single transfer. This require that drivers such as m25p80 has to be modified, but this is outside the scope of this issue. It is purely for optimization.