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I tried to work with 10/100Mbs ethernet interface in the DE1-SoC board. After a while, I found that the KSZ9021RN PHY chip (the PHY chip used in the DE1-SoC board connected to the HPS of the Cyclone V) has two alternatives to manage the speed: (1) the MII interface for 10/100Mbps and (2) GMIII for 1Gbps. Both alternatives have specific pins in the PHY chip that have to connected to the Cyclone V. For instance, one of these pins is the transmit clock: (1) TX_CLK for MII interface and it is an input for the MAC and (2) GTX_CLK for GMII interface and it is an output for the MAC.
From the datasheet of the PHY I cannot find a way to manage the ethernet speed according the GTX_CLK. The ethernet speed is changed changing the interface from MII to GMIII. This is not the way that the standard defines the GMII interface.
Unfortunatelly, in the DE1-SoC board, only the GTX_CLK signal is connected and consequently I cannot know how the PHY chip can be used in 10/100Mbps.
Conclusion: the DE1-SoC does not support 10/100Mbps or I am missing some information from the board schematics.
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Yes, I believe you are right. I also remembered reading that Cyclone V SoC does not support RMII PHY through the HPS Pins (RMII is only supported if exported to the FPGA fabric) in the erratum before.
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