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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Cyclone V FPGA-to-HPS Bridges design example bug?

I found what appears to be a bug in the example_design.c file, but didn't see a means to report it directly. So, I'm posting it here.

example_design.c:233 

    for(int i=0; i<test_set->hardware_instances; i++)
    {
        test_set->bg_counters = 0;
    }

should be 

    for(int i=0; i<test_set->hardware_instances; i++)
    {
        test_set->bg_counters = 0;
    }

(see https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html)

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Hi,

    Thanks for notifying the bug, let us check/workaround it.

    We will get back to you on this as soon as possible.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)