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Altera_Forum
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7 years ago

Cyclone V FPGA-to-HPS Bridges design example bug?

I found what appears to be a bug in the example_design.c file, but didn't see a means to report it directly. So, I'm posting it here. example_design.c:233 for(int i=0; i<test_set->h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi,

Thanks for notifying the bug, let us check/workaround it.

We will get back to you on this as soon as possible.

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)