Honored Contributor
Honored Contributor--- quote start ---
1) can i simply clock down the sdram to 25mhz?[/b]
--- quote end ---
yes, you will see a clk to the external sdram, which comes from e0 of sdram_pll.
you will have to match the sdram controller clk to 25mhz too.
<!--quotebegin-queisser@Nov 2 2005, 11:06 AM 2) what about the phase shift of -63 in the sdram pll, does it have to change to a different angle at 25mhz? --- Quote End --- The phase shift needs to be specific in absolute time. Get the phase shift time in "ns" for the 50MHz design, which should be "-4.8ns" if i remember correctly, and set that for the new 25MHz clock. --- Quote Start --- originally posted by queisser@Nov 2 2005, 11:06 AM 3) what about the "connector.pll"? i changed it to 25mhz as well but it seems like it wouldn't affect anything --- Quote End --- The cyclone device has some hardware specific connections which needs to be there, and the connector pll is one of them. --- Quote Start --- originally posted by queisser@Nov 2 2005, 11:06 AM 4) the "sysclock" (c0 output) of the connector_pll seems to be unused. is it needed for anything? --- Quote End --- Check the pin assignments editor, if it is not connected to anything, then it probably is unused. Btw, my designs have shown that the JTAG_UART needs to be at 50MHz for the nios2-terminal to work correctly. Anyone can get it working at other frequencies?
