Honored Contributor
Honored Contributor--- quote start ---
1) can i simply clock down the sdram to 25mhz?[/b]
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maybe. it's already clocked down, and i'm pretty sure that sdram is not static logic. you could just remove the sdram from your system...?
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originally posted by queisser@nov 2 2005, 11:06 am
2) what about the phase shift of -63 in the sdram pll, does it have to change to a different angle at 25mhz?
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that will probably need tweaking. it's not used as a phase shift as much as a time delay, so if you halve the frequency, you'll probably have to halve the phase shift, too, to keep the same time delay.
<!--quotebegin-queisser@Nov 2 2005, 11:06 AM 3) what about the "connector.pll"? i changed it to 25mhz as well but it seems like it wouldn't affect anything --- Quote End --- PLLs don't really use "MHz" as their settings, they use clock multiplier and divider factors... so are you saying you changed it to a 1/2? Have you tried getting a 25 MHz oscillator and dropping it in? As a side note, I remember seeing notes that things like the flash programmer didn't work below 50 MHz. --- Quote Start --- originally posted by queisser@Nov 2 2005, 11:06 AM 4) the "sysclock" (c0 output) of the connector_pll seems to be unused. is it needed for anything? --- Quote End --- I think it used to be used for the debugger port back in Nios I. If you don't hook it up, it gets optimized away.
