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riba's avatar
riba
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2 years ago

Cyclone III - Timing Constraints Issue

I encountered an issue with softcore firmware and FPGA setup on a Cyclone III device. Previously, I had been experiencing problems with FPGA synthesis, particularly in meeting timing constraints. In...
Nios Architecture
riba's avatar
riba
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2 years ago

Hi,

Could it be possible that we are experiencing one of the issues from this document -> https://statics.teams.cdn.office.net/evergreen-assets/safelinks/1/atp-safelinks.html, either:

-M9K Memory Block Read Issue

-External Memory Specification for DDR2 SDRAM

Can you confirm that this is possible and how could it be fixed?

Thanks