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riba's avatar
riba
Icon for New Contributor rankNew Contributor
2 years ago

Cyclone III - Timing Constraints Issue

I encountered an issue with softcore firmware and FPGA setup on a Cyclone III device. Previously, I had been experiencing problems with FPGA synthesis, particularly in meeting timing constraints. In...
Nios Architecture
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


Since you have solved your timing issue and are seeing hardware is working as expected, similar problems won't occur.


It is important to ensure your timing constraints correctly describes the timing paths and that the timing violations are solved in all corners of the FPGA. This is to ensure the hardware works as expected.


Regards,

Nurina


p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.