Honored Contributor
Honored ContributorI would recommend against "hacking" the generated Verilog or VHDL. If you do this, everytime you run SOPC Builder, you'll need to make your changes all over again. Instead, make a top-level design that instantiates the SOPC module & FIFO and connects the two. That way, as long as you don't make changes to the exported ports from SOPC Builder, you won't have to redo any code changes.
--- Quote Start --- originally posted by cjike@Nov 17 2006, 02:13 PM thanks for the fast response!
what is the "standard" way to integrate an altera "scfifo" with a multiprocessor nios ii system with custom instructions?
would i do the following:
1. use sopc builder to add ci with extra fifo interface to some nios ii processors
2. hack generated verilog to instantiate scfifo, connecting it to the "extra" ci ports that are exported to the top level
3. compile the hacked verilog in quantus
or are there some quantus functions/menu options that could help with this?
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