Custom Instruction writing to FIFO

Thanks for the fast response!

What is the "standard" way to integrate an Altera "SCFIFO" with a multiprocessor NIOS II system with Custom Instructions?

Would I do the following:

1. Use SOPC Builder to add CI with extra FIFO interface to some NIOS II processors

2. Hack generated Verilog to instantiate SCFIFO, connecting it to the "extra" CI ports that are exported to the top level

3. Compile the hacked verilog in Quantus

Or are there some Quantus functions/menu options that could help with this?

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originally posted by badomen@Nov 17 2006, 10:03 AM

if you have extra ports declared "export" then they should show up at the top level of your sopc builder system and not directly in sopc builder. sopc builder will show you known interfaces like avalon slave, master, tri-state.

by altera fifo i assume you mean "scfifo" or "dcfifo"? if it doesn't have an avalon slave interface it will not show up in sopc builder. but you can run the logic through component editor and give it an avalon interface (so you just need to "bundle" it as a component)

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