Your code doesn't have parameters (I don't know the exact equivalent of "generics" in Verilog) and that's why your parameters list is empty in the component wivard.
In the example shown on the page you linked, the code they used had multiple parameters, and that's why they appeared on the list.
Having an empty list in your case is perfectly normal, you can carry on and create your custom instruction.
Edit: I never made any custom instruction, but I find it strange that you never set the value of the 'done' output. Instead you seem to be using it as an input...