Custom Instruction addition

Hi

The code is direct as i just took the template of Multicycle logic code

given in quartusII installation directory

and added a simple direct logic to it

// Verilog Custom Instruction Template File for Multi-cycle Logic

module custominstruction(

clk, // CPU system clock (always required)

reset, // CPU master asynchronous active high reset (always required)

clk_en, // Clock-qualifier (always required)

start, // Active high signal used to specify that inputs are valid (always required)

done, // Active high signal used to notify the CPU that result is valid (required for variable multi-cycle)

dataa, // Operand A (always required)

datab, // Operand B (optional)

result // result (always required)

);

//INPUTS

input clk;

input reset;

input clk_en;

input start;

input [31:0] dataa;

input [31:0] datab;

//OUTPUTS

output done;

output [31:0] result;

reg [31:0] temp;

reg[31:0] result;

// custom instruction logic (note: external interfaces can be used as well)

always@(posedge clk,posedge reset)

begin

if(reset)

result <= 32'b0;

else

if(clk_en)

begin

if(start)

temp <= dataa+datab;

else if(done)

result <= temp;

end

end

endmodule

regards

M Kalyansrinivas