Custom FIFO read in Nios IDE

A slightly separate issue.

Give your fifo a 32bit interface. Since the fifo itself is 16bits wide set the high bits to zero on reads.

As defined you'll find that the actual span is 4 bytes and you'll see two read cycles for every access (the second one will have a different address). Since the nios cpu always asserts all 4 byte enables for reads, both reads will have both byte enables asserted.

If you do a 16bit write, one of the writes has no asserted byte enables.

I'm not sure the order of the accesses is defined either.