Creating SOPC-aware DMA slave device

Hi Brad,

I think there are some app notes from www.altera.com. Also, if you reference the Avalon Bus Specification that will help.(AN-333 Developing Peripherals for SOPC Builder)

Creating a custom SOPC component is easy if you use the wizard in SOPC builder. Just build the interface as you would any interface. Then whether you are using VHDL or Verilog, the wizard will help you match port names for an Avalon component to your component. Any port name that does not match up is defined as an EXPORT type of signal.

The FIFO is easy to hook up if you use streaming data. The signals READYFORDATA and ENDOFPACKET are all that are needed (in addtion to normal slave signals) to implement a streaming transfer.

Make the FIFO signals qualify READYFORDATA,

Example( In Verilog):

assign readyfordata = ((fifo_cnt < 10&#39;d1000) && (pixel_count < (800*600)) && (!sync_end_of_picture)) ? 1&#39;b1 : 1&#39;b0;

Where fifo_cnt is straight from the FIFO_DC component.

A few more tips:

1) I found when using the DMA to stream data you need to minimize the WRITE latency for your component. I can&#39;t remember off hand what the value is , either 1 or 0 waits.

2)Also, use the Nios sim ( AN-351), it was INVALUABLE in debugging a real DMA transfer. If you take this approach, you may want to preload data in your SDRAM for simulation, otherwise a simualtion will take forever. I wrote a nice little perl script that is referenced somewhere in the forum that will help.

3) Use the HAL paradigm to program the DMA. It is clean and works fine for Nios 5.0 and Quartus 5.0.

Hope this info is helpful.

-Baycool