Forum Discussion
Altera_Forum
Honored Contributor
9 years agoActually I thought that there would be a ready made "terminal window" into Nios-II design accesible from Quartus or Eclipse or some reference design.
Looking at this it seems this is a custom solution. I think there is something about tcl commands that can be used to debug Qsys or SOPC designs, basically we write some tcl command into a command window aka terminal and it transmits something to the design on the FPGA to read/write memory locations. Don't know that details though, I was expecting a response along those lines. I mean it does not have to be the humble serial port, I think that this should be possible via the byte-blaster JTAG interface too.