Creating a Ibex component in platform designer on Arria 10 FPGA development board

Hi TingJiangT ,

I developed a component (myriscv) with the AXI4 Manager bus for Instruction & Data Manager and internally assigned to clock, reset, and this is the master. When I try to connect to the JTAG UART IP and on chip memory IP as slaves, I got the following issues:

Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.dm_axi4_master->null
Error: riscvcomp: Connection (post-transform) is missing an end point: riscvcomp_myriscv.im_axi4_master->null
Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null
Error: riscvcomp: Connection (post-transform) is missing an end point: clock_in.out_clk->null
Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_jtag_uart.avalon_jtag_slave
Error: riscvcomp: Connection (post-transform) is missing a start point: null->riscvcomp_intel_onchip_memorry.s1
Error: Internal Error: Cannot generate a system with dangling connections.

Please look the screenshot attached for the reference.

Please suggest the needful to be done.

Thanks,

Nikitha