Constraining Nios Design

BadOmen,

I have a Nios II design similar to the bup design found in CIII 3c120 Ethernet Standard design. For those set_input_delay and set_output_delay constrains applied to ext_flash input and output signals such as fsm[a], fsm[b] and etc, how can I determine the value of its delay? Do I always need to create a virtual clock or I can reference to osc clk as shown

set_output_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {fsm_a

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set_input_delay -clock [ get_clocks clkin_50 ] 2 [ get_ports {fsm_d

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Is the delay '2' determined by clkin_50? What if I have an osc clk of 125MHz?

Thanks