Constraining Nios Design

Those JTAG constraints can be found in the Quartus II templates menu (open your .sdc file, click the edit toolbar-->templates, then dig around the SDC section and you should find what you need for the JTAG interface).

I wouldn't worry about the paths within the FPGA for now since those are most likely caused by some of your I/O not be constrained. For example, focus on getting fsd constrained (I'm assuming that's your bidirectional tri-state data signal) and less on the logic it is connected to. With bidirectional signals you need to specify input and output constraints, if I remember correctly this is done with the --add_delay argument for the additional direction.

I would take a look at some existing design examples and see how they are constrained. Don't just blindly copy and paste the constraints over since they are board specific, but that should give you an idea of what to do.