Constraining Nios Design

Ok thanks, sounds like a good way to start. I had a CPU reset and some push button i set as false path now. But there are still a lot of signals I can't determine what they are actually for. I descripted it in the following paragraph, but it might be easier to just lock at the table. So i attached a zip file with the unconstrained input and output paths. Could you tell me what these signals are for? How I do i get the constrain timing for the ones i cant set as false paths?

Thanks very much.

Then there are a lot of signals coming from "altera_reserved_tdi" and "altera_reserved_tms" going to some jtag stuff and a sld_hub:auto_hub. No idea what that is!? Another big chunk is something called fsd (16bit width) going to my flash tristate bridge|tcm_data_in_req. ideas on that? And then there is some ethernet signals enet_mdio to some req_data_rd and enet_rx_dv as well as enet_rxd(4bit) going to soe auto_generated|input_cell_l/h.