Constraining C compiler to not make byte accesses to PCIe

Ok I have some more information ... RC memory contains a list of control blocks that are all the same length and reside of 4byte aligned boundaries.

... Each control block is made up of a structure where elements of the structure may or may not be used depending on what task the control block specifies.

.... It seems the NIOS compiler is making some optimizations on which element of the control block structure are required and optimizing out the complete read.

... This results in byte accesses that the 128 bit HIP interface doesn't support.

I'm Ok with any compile optimization, if that is the cause, but would like to be able to specify a non optimization flag at compile time.

I have suggested the NIOS II code could defeat the compiler optimization by forcing some dummy read of each control block to a local copy ... this may work.

The SW team will again try incase anything has changed and I can trap any non 4 byte Inbound reads on the PCIe analyzer.

Thanks, Bob.