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Altera_Forum
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10 years ago

Constraining C compiler to not make byte accesses to PCIe

The Stratix 128 bit AVMM I/F to HIP is broken for certain byte enable combinations including byte. Resulting in a malformed TLP. I have a workload in RC host memory that the NIOS II fetches and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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The software on the other end of the link needs to be changed to never use unaligned addresses for requests for FPGA processing. I.e. never give the FPGA an unaligned address for it's data pointer.

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Thanks Galfonz, I will check with SW team but I believe the pointer to the head of the descriptor chain is aligned , but the structures in the chain are random structure lengths and as NIOS processes the workload, the compiler makes some optimizations resulting in byte accesses that result in the malformed TLP ... let me check why the SW team on why can't all the fetches from NIOS of the workload to be aligned and be 4 byte.