Configuring TSE & Nichestack

This just make no sense.

In my main vhdl file i'm exporting sysclk.c3 as PHY clock (25 MHz since i'm using MII).

If i set the sysclk PLL as normal pll, i get the warning "Critical Warning (176598): PLL "nios:nios_inst|sysclk:the_sysclk|sysclk_altpll_l4h2:sd1|pll7" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_F2"" but ethernet works as expected (all timings meeted)

If i set the PLL in "no compensation" mode, all timing are meeted but the ethernet stucks at DMA loop