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Honored Contributor
Honored ContributorConfiguring TSE & Nichestack
I have Quartus&SBT 11.1, and a board with PHY 83848. I cannot bring up the eth interface with simple socket example. SOPC configuration is good (i hope), but i can't initialize the software: ...
Altera_ForumHonored Contributor
Honored ContributorThis just make no sense.
In my main vhdl file i'm exporting sysclk.c3 as PHY clock (25 MHz since i'm using MII). If i set the sysclk PLL as normal pll, i get the warning "Critical Warning (176598): PLL "nios:nios_inst|sysclk:the_sysclk|sysclk_altpll_l4h2:sd1|pll7" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_F2"" but ethernet works as expected (all timings meeted) If i set the PLL in "no compensation" mode, all timing are meeted but the ethernet stucks at DMA loop
