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Altera_Forum's avatar
Altera_Forum
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13 years ago

Configuring TSE & Nichestack

I have Quartus&SBT 11.1, and a board with PHY 83848. I cannot bring up the eth interface with simple socket example. SOPC configuration is good (i hope), but i can't initialize the software: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Ok then the reason will be more difficult to pinpoint. I suggest to put signaltap probes on all the interfaces around the SGDMAs to try and figure out what it is trying to do when it is stuck.

Did you connect all 6 SGDMA masters directly to the memory, without pipeline bridges? What frequency are you using for the system clock? Does your design meet timing requirements?

When I run a design at 100MHz I have a hard time meeting timing requirements with 8 masters (6 from the DMAs, 2 from the Nios) connected to the RAM directly and I have to use 1 or 2 pipeline bridges.