Configuring FPGA through EPCS (EEPROM) INCLUDING Nios II program?

If you use the EPCS boot code you'll also need the instruction cache (you can't use tightly coupled memory for it).

If nothing else needs access to your code/data space then tightly couple it as both code and data memory.

There is no point at all using either cache for on-chip memory.

(It really ought to be possible to tightly couple both the JTAG code and the EPCS boot code.)

My example is a two cpu system, loaded over PCIe. It is real code and those are the correct sizes.

The original plan was to tightly couple the 'shared_data' to both cpu, but it is useful to be able to read it over PCIe for diagnostics so one of the cpus takes the slight performance penatly of Avalon transfers.