Configure NIOS firmware burning interface

I understand you have many questions, and it's great that you're exploring the Nios II and FPGA ecosystem in detail. To help you more effectively, I’ve compiled a list of official documentation and resources that cover your topics thoroughly:

Intel Nios® II Processor Handbook
https://www.intel.com/content/www/us/en/docs/programmable/683127/latest/overview.html

Covers architecture, boot flow, interrupts, memory setup, and more.

Platform Designer (Qsys) User Guide
https://www.intel.com/content/www/us/en/docs/programmable/683092/latest/overview.html

How to build systems, assign IRQs, connect peripherals, etc.

Nios II Hardware Development Tutorial
https://www.intel.com/content/www/us/en/docs/programmable/683125/latest/introduction.html

Step-by-step project, JTAG UART, IRQ config, ROM/RAM settings.

Configuring Intel® FPGAs Using JTAG
https://www.intel.com/content/www/us/en/docs/programmable/683209/latest/jtag-interface.html

JTAG basics, pin names, hardware setup (TCK, TDI, TMS, TDO).

Embedded Booting Options on Intel® SoC FPGAs
https://www.intel.com/content/www/us/en/docs/programmable/683184/latest/overview.html

Explains boot ROM, bootloader, firmware loading process.

Cyclone 10 LP Device Handbook
https://www.intel.com/content/www/us/en/docs/programmable/683157/latest/cyclone-10-lp.html

For checking internal RAM sizes, flash options, and device-specific info.

These should give you a solid foundation and answer most of your current and future questions. I'd recommend going through them first, they’re very detailed and well-structured.