Altera_ForumHonored Contributor21 years agoConcatenate 3 memory bank into one I have a question related to the way how NIOS IDE (or the linker beneath it) does see ram for program/data allocation. I have designed a nios II board with 3 external SRAM banks, they consist o...Show More
Altera_ForumHonored Contributor21 years agoHave you looked in the documentation? Have you solved this?
Recent DiscussionsDK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery failsWhere is FreeRTOS-Plus-TCP DesignSolvedNIOS V: Systick based timeouts not available when using internal timerSolvedAshling RISC Free IDE fails to download ELF fileNIOS V/m dbg_reset_out signal (Q25.1 Std, MAX10)