Component Editor

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originally posted by leszekd@Mar 31 2006, 02:28 PM

hi,

why i can't use more than one chipselect for avalon slave in component editor? in user interface tool it i can use more than one chipselect. i2c opencore have two chipselects (wb_stb_i andwb_cyc_i). any idea?

thank you

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=13947)

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In wishbone terms, the signals wb_stb_i and wb_cyc_i have difference meaning.

wb_stb_i - strobe data(data is valid)

wb_cyc_i - current cycle of access is valid

However, I solved this dilemma like this

chipselect from avalon is connected to wb_stb_i and wb_cyc_i

That is all!

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originally posted by slava+mar 31 2006, 09:19 am--><div class='quotetop'>quote (slava @ mar 31 2006, 09:19 am)</div>

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<!--quotebegin-leszekd@Mar 31 2006, 02:28 PM

hi,

why i can&#39;t use more than one chipselect for avalon slave in component editor? in user interface tool it i can use more than one chipselect. i2c opencore have two chipselects (wb_stb_i andwb_cyc_i). any idea?

thank you

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=13947)

--- quote end ---

--- Quote End ---

In wishbone terms, the signals wb_stb_i and wb_cyc_i have difference meaning.

wb_stb_i - strobe data(data is valid)

wb_cyc_i - current cycle of access is valid

However, I solved this dilemma like this

chipselect from avalon is connected to wb_stb_i and wb_cyc_i

That is all!

<div align='right'><{post_snapback}> (index.php?act=findpost&pid=13950)</div>

[/b]

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I don&#39;t think you can do this anymore; as the original poster said, you can only use one chipselect. I tied them internally in the verilog code and then just used one chipselect.

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif

Of course you can have a lot of chipselects. i do this very often to get different memoryspaces, datawidths, multiple interrupts ...

how ? as i had posted that before, it is mentioned inside alteras literature ...

first thing is you must use the signal naming as altera recommends them.

biggest goal if you do so is that you will never get problems again with the interface and signal tabs inside the component editor.

start the nameming with avs (avalon valid slave) or avm (avalon valid master) or gls (global signal) or .... there is another one for tristate but can&#39;t get it right out of my head ... excercise read the manual :-)))

then follows a _custominterfacename_ like _myinterface_ or _anotherinterface_

after this you type the signal name like address or data or byteenable.

so you module can be like this

gls_reset

gls_clk

avs_my1device_chipselect

avs_my1device_address

avs_my1device_readdata

avs_my1device_read

avs_my1device_waitrequest

avs_my1device_int

avs_my2device_chipselect

avs_my2device_address

avs_my2device_readdata

avs_my2device_read

avs_my2device_waitrequest

avs_my2device_int

and if you want to have signales outside sopc just insert an "export" like

avs_my2device_export_thissignalsistobeexported

if you do so, sopc will automatically generate 2 interfaces for the above modul

my1device

my2device

the only thing that is anoying is that each interface can have only 1 int signal.

i wish altera will remove this and enable it .... nios2_60 seems to be very near :-))) .... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/blink.gif

remember ... always obay the waitrequest. ... always include signals that need to be used .... avm needs its own clock avm_mymaster_clk if you use any other clock you will have problems. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif