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Altera_Forum
Honored Contributor
16 years agoCompiling NIOS system in Quartus II 9.1
Hey all,
New Altera user here. I generated a system in SOPC Builder. The result was a bunch of verilog files. I then proceeded to Quartus for Analysis & Synthesis. I added all the verilog files produced by SOPC Builder to my current project (Project > Add/Remove Files in Project). I then imported my pin assignment file. When I try to perform Analysis & Synthesis, I get these errors: Verilog 2001.
Error (10170): Verilog HDL syntax error at uclinux_nios_inst.v(3) near text "("; expecting ";"
Error (10839): Verilog HDL error at uclinux_nios_inst.v(2): declaring global objects is a SystemVerilog feature SystemVerilog
Error (10170): Verilog HDL syntax error at uclinux_nios_inst.v(3) near text "("; expecting ";" Contents of uclinux_nios_inst.v
//Example instantiation for system 'uclinux_nios'
uclinux_nios uclinux_nios_inst
(
.address_to_the_cfi_flash_0 (address_to_the_cfi_flash_0),
.clk_0 (clk_0),
.data_to_and_from_the_cfi_flash_0 (data_to_and_from_the_cfi_flash_0),
.read_n_to_the_cfi_flash_0 (read_n_to_the_cfi_flash_0),
.reset_n (reset_n),
.select_n_to_the_cfi_flash_0 (select_n_to_the_cfi_flash_0),
.write_n_to_the_cfi_flash_0 (write_n_to_the_cfi_flash_0),
.zs_addr_from_the_sdram_0 (zs_addr_from_the_sdram_0),
.zs_ba_from_the_sdram_0 (zs_ba_from_the_sdram_0),
.zs_cas_n_from_the_sdram_0 (zs_cas_n_from_the_sdram_0),
.zs_cke_from_the_sdram_0 (zs_cke_from_the_sdram_0),
.zs_cs_n_from_the_sdram_0 (zs_cs_n_from_the_sdram_0),
.zs_dq_to_and_from_the_sdram_0 (zs_dq_to_and_from_the_sdram_0),
.zs_dqm_from_the_sdram_0 (zs_dqm_from_the_sdram_0),
.zs_ras_n_from_the_sdram_0 (zs_ras_n_from_the_sdram_0),
.zs_we_n_from_the_sdram_0 (zs_we_n_from_the_sdram_0)
);
Thank you.3 Replies
- Altera_Forum
Honored Contributor
So here is what I did, I removed uclinux_nios_inst.v from my project and attempted to compile again. No errors, albeit some warnings. I set the top level entity as nios_system.v (assuming this is the name of the NIOS system which was made in SOPC Builder). I did not make an top-level verilog netlist file nor bdf file. After compilation, I used the RTL view and everything looks connected. Does this sound right, or do I need that bdf or make a top-level verilog netlist?
- Altera_Forum
Honored Contributor
I believe that the <sopc module name>.qip file is all that you will have to add to the project as that contains all the SOPC files used to generate and it will be updated each time you generate so it stays current.
- Altera_Forum
Honored Contributor
Hey User_Void,
Did you ever resolve this problem? Thanks! -Jorden