Forum Discussion
Altera_Forum
Honored Contributor
20 years agoHi Nir,
We have seen similar behavior, and it stems from the fact that to operate in True IDE mode, CF cards need their atasel_n pin driven low at power-up. Since atasel_n is an FPGA I/O, and the FPGA's I/O are tri-stated before FPGA configuration, we need to power-cycle the compact flash cards from Nios during the boot process to ensure that the CF card initializes correctly. However, compact flash cards from certain manufactuerers exhibit significant leakage current. This causes them not to be powered off completely when the CF power register bit in the CF peripheral is cycled by the Nios II CPU, and as such, the atasel_n input isn't sampled again as happens during the power on process. The following web page describes the problem in more detail and a couple of potential workarounds: http://www.altera.com/support/ip/processor...-er.html#boards (http://www.altera.com/support/ip/processors/nios2/ips-niosii-50-er.html#boards) In the future, we may modify dev boards to have the atasel_n pin as a stuff option to prevent this.