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AKhed's avatar
AKhed
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7 years ago

Clock signal jumper connection

Hello, I am designing Main board using Altera FPGA. In circuit I need external differential clock. On main board I have introduce one clock generator circuit also have provision to take clock from e...
AKhed's avatar
AKhed
Icon for New Contributor rankNew Contributor
7 years ago

Hello Anand,

As I need to interface two source on same differential clocks pin for every clock in available on FPGA and at a time one is present. In my application is clock in either from on board clock generator or from external board and choice is for user who interfacing external board. So, I can't connect both clock source to FPGA. I will check with clock multiplexing IC, still it will increase lot of hardware as I have 4 clock input signals.

Does berg pin harm in this condition? if yes what are the different effect on signal can you explain.

if I directly merge the signals what are the different effect of same.

As I have seen lot of board on which berg pin jumper is used for selection clock source but it have smaller frequency range like 5Mhz. one of the reference from microchip is here.

https://www.microchip.com/webdoc/stk500/stk500.clock.settings.html