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Altera_Forum's avatar
Altera_Forum
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15 years ago

CIII/EPCS design configures and programs but does not start

Hi,

I have a design with EP3C40 and EPCS64. I create flash files with:

sof2flash --epcs --compress --input=logic.sof --output=logic.srec

elf2flash --epcs --after=logic.srec --input=software.elf --output=software.srec

cat logic.srec software.srec > all.srec

I then program the EPCS64 with:

nios2-flash-programmer --epcs --base=0x40000800 all.srec

It all programs and verifies fine. I power cycle the board and the processor doesn't come up. However, if I do:

nios2-flash-programmer --epcs --base=0x40000800 --go

then it starts, so obviously it programmed the EPCS correctly, the FPGA configured at start and it loaded the software. It just didn't start.

My reset vector points to the base of the EPCS device. Tools are Quartus 10.1 SP1 and NIOS IDE 10.1 SP1.

I've done exactly the above on other devices before with no problem but this is my first CIII design. Any clues?

Thanks,

Mark.

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Hi Mark.

    I think you definitely have a problem with the Nios 2 bootloader.

    I'd recommend you check the hex file and possibly regenerate it from the source files.

    --- Quote End ---

    Yeah, I wondered the same thing. The project was from scratch, so there's no old cruft in there. However, just to be sure I wrote a little program to read back the bootloader bytes from the EPCS component. It matches byte for byte with the ciii hex file in the Quartus directory, so is good I think.

    --- Quote Start ---

    I attach for your convenience my CIII bootloader file. It should work for you, too.

    Execute a fpga MIF update, flash into epcs and let me know if this solves your problem.

    --- Quote End ---

    Thanks. I'll give it a go.

    Mark.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    Presumably the boot loader has the address of the rom and memory compiled into it - they could be wrong ...

    --- Quote End ---

    Possibly, although as I wrote in the original post if I power up the board, connect the JTAG lead, and do:

    nios2-flash-programmer --epcs --base=0x40000800 --go

    then the software starts fine. This suggests to me that the boot loader has copied the code to the RAM correctly but has not performed the final call to the start of the software properly.

    Mark.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Okay, I figured out what was going on. My board has a reset circuit that holds everything in reset until the supplies are stable. However, it turns out it doesn't monitor the SDRAM supply. So I think what was happening was the FPGA would configure and start the boot loader which would then copy the software into the not-quite-ready SDRAM. I added a delay to the release of reset and now it comes up reliably.

    Mark.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The SDRAM will need several (refresh?) cycles [1] after poweron before it will hold data. The SDRAM controller probably does these - but they'll take a few clocks.

    [1] Well EDO DRAM needed them, which meant the software had to perform them before doing anything else.