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Altera_Forum's avatar
Altera_Forum
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13 years ago

Changing Nios Clock Frequency on a De0 nano board

Hi, I've got a design including a Nios 2 working on my De0 nano board. I read the tutorials for setting up a Nios 2 in Qsys, I just added some more pio for my signals. I'm also using the SDRAM,...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi Linas,

The PLL is a mega function in my verilog code, that is working correctly because I can see it on an output pin.

I've actually managed to resolve the issue by starting a new project in eclipse and pasting my existing code in. It's almost as if the generate BSP function doesn't do what it's supposed to (or what I think it does) after changing the hardware.

Thanks for all your help anyway!