Can not understand TIMEQUEST cookbook tSU, tH, and tCO Constraints need help

Thank you very much kaz, that's an excellent explanation.

I have a another question, would you help me? I'm kind of stuck here for days.

This is reports generated by TIMEQUEST "Report Datasheet".

Here is the question:

1. How can I calculate tSU, tH, and tCO from rise & fall in this report?

2. What does this rise and fall mean or represent for?

Setup Times

Data Port    Clock Port    Rise    Fall    Clock Edge    Clock Reference
SDRAM_DQ
    CLKIN_50M    3.776    3.951    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.754    3.929    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.766    3.941    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.766    3.941    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    3.740    3.915    Rise    u1|altpll_component|auto_generated|pll1|clk

Hold Times

Data Port    Clock Port    Rise    Fall    Clock Edge    Clock Reference
SDRAM_DQ
    CLKIN_50M    -3.122    -3.297    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.153    -3.328    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.165    -3.340    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.165    -3.340    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_DQ    CLKIN_50M    -3.139    -3.314    Rise    u1|altpll_component|auto_generated|pll1|clk

Clock to Output Times

Data Port    Clock Port    Rise    Fall    Clock Edge    Clock Reference
CORE_CLK    CLKIN_50M    0.900        Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A
    CLKIN_50M    0.823    0.796    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.818    0.791    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.818    0.791    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.823    0.796    Rise    u1|altpll_component|auto_generated|pll1|clk
SDRAM_A    CLKIN_50M    0.813    0.786    Rise    u1|altpll_component|auto_generated|pll1|clk