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Altera_Forum's avatar
Altera_Forum
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10 years ago

Can I connect c0 and c1 from ALTPLL directly to pins in MAX10?

Hi all, I'm want to test the PLL outputs for a nios system in a MAX10 fpga. I was told in another thread that I needed to add a clock bridge to simultaneously connect the output (c0 or c1) inte...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Yes, it is perfectly valid to connect both c0 & c1 to device pins. If you're struggling I suggest you post (the source code for) your project and we can have a look. Zip up the .qsf, .qpf, .qsys and any verilog/vhdl files you're using.

Cheers,

Alex