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Altera_Forum
Honored Contributor
Honored ContributorBurst transfer from memory to Nios II
Hello, I have a hard time understanding how the Nios II handles memory accesses. In our Nios II design we want to use burst transfers to transfer data from SRAM into the caches of the proc...
Altera_ForumHonored Contributor
Honored ContributorMy slave exposes a memory interface to the Nios II processor. The width of the data bus is 32 bits and the number of pending read transactions can be set by generics.
There are also other devices attached to the data bus like SRAM and DDR2 memory (I'm developing on a Altera Embedded Systems Development Kit, Cyclone III Edition). The SRAM is not used currently but for the target platform we have designated SRAM as main memory. Does the DDR2 SDRAM Controller with ALTMEMPHY support burst transfers? There doesn't seem to be any documentation for Qsys. I've only seen a datasheet for the MegaWizard.
