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Altera_Forum's avatar
Altera_Forum
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14 years ago

Burst transfer from memory to Nios II

Hello, I have a hard time understanding how the Nios II handles memory accesses. In our Nios II design we want to use burst transfers to transfer data from SRAM into the caches of the proc...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

When bursting is enabled in the cache settings, the following burst lengths are used:

Instruction master burst length = 8 (32-bit wide beats)

Data master burst length = 4/8 (32-bit wide beats base on cache line size of 16/32 bytes)

For SRAM accesses enabling bursting on the CPU side doesn't buy you anything since the memory doesn't support bursting. Whether using a DMA makes sense depends on the algorithm you are implementing. If your code works on small buffers of data that fit in an onchip RAM then it might make sense to DMA the data from ofchip SRAM (I'm assuming you are using SRAM and not SSRAM) and access it as tightly coupled memory. If you are doing short quick accesses then the overhead of moving the data with a DMA is probably not worth the effort.