Burst transfer from memory to Nios II

You have to set 'enable burst' on the cache memory to get cache-line sized memory bursts for cache line fill/writeback.

Memory cycles to tightly coupled memory and cache hits complete in 1 cycle, but the data value (for reads) can't be used in the next two instructions (cpu stalls if you try to do this).

Memory cycles over the Avalon bus are synchronous on the processor (ie it stalls until the slave cycle finishes), the two cycle delay then applies to reads.

I'm sure it wouldn't have been that difficult to give the option of 'posting' a single write. Aynchronous reads would be slightly more difficult (due to scheduling the write into the register file).