Buffering Avalon tristate data bus

Hi BadOmen & Jesse,

My original idea was to create an avalon slave (not tristate) together with some logic and merge it into the tristate side of the bus. There is a simplified diagram showing the basics what I've tried to do:

... see diagram ... (http://www.ing-buero-ruettger.de/nios/databus.htm)

But if you look at the cyclone IOE structure, there is no physical way to insert these buffers. As Jesse posted, it is part of the "avalon to tri-state bridge" to merge input- and output-lines into a single bidir signal which is part of the IO cell. My design has to be done in the inner part of the tristate bridge.

I think one possibility is to create an own avalon-to-tristate-bridge with a multiplexer and tri buffers, controlled by the appropriate CS signals.

Thanks all for your help.

Mike