Buffering Avalon tristate data bus

Hi BadOmen,

On my Avalon Tristate Bus there are several off-chip devices sharing Address, Data, RD and WR . But all of them have their own CS and every device only drives the bus while its CS is active. This works so far.

One external device is a bank of DSPs producing lots of data via a 16-Bit-Interface readible in two adjacent byte accesses (on an add-on board with 8-bit data bus). Reading these two bytes is possible either in memory-mode with Avalons dynamic bus sizing, or in register mode with software overhead reading (Addr + 0) and (Addr + 4) plus combining both bytes to a halfword. In dynamic mode, a 16-Bit-read accross a 8-bit interface on a 32-bit data-bus results in four single read cycles. This will increment an address counter in the DSPs by four instead of two. So both variants offer a bad performance and / or a malfunction in the DSP-Interface (HPI8).

My idea was, to use a 16-bit avalon register interface with some additional glue logic which accesses two bytes and exchanges halfwords with nios (waitrequest is needed). Reading is not the problem, because the DSPs doesn't drive D[15..8]. But when writing to DSPs all data-lines are in active state driven by avalon bus. This is where I thought on adding tri-state buffers to substitute D[7..0] in a second cycle with the data provided on D[15..8].

But meanwhile I've looked at the pin-logic in cyclone devices. There is no single bidirectional tri state line possible. Output to the pin is done via a tri-state buffer. Input from this pin is made behind this buffer, directly at the pin. So this results in two separate lines: one for input and one for output (via tri). A data signal, configured as 'inout' is already the pin itself! You cannot insert additional logic.

Perhaps I need two interfaces: one for reading and one for writing. Important is the read path, which will be controlled by a DMA to get most possible performance, writing could be done in a slower mode.

Mike