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Andrew099's avatar
Andrew099
Icon for New Contributor rankNew Contributor
2 years ago
Solved

BSP fails to build for FreeRTOS on a Nios V with UART

I have a Nios V on a Max 10 with a UART (RS-232 Serial Port) Intel FPGA IP (and also JTAG UART). When I opened up the BSP editor, I selected FreeRTOS and went with all the defaults and made a BSP. However, when I try building a bare bones hello world C program, the BSP fails to build. It says that the BSP source file altera_avalon_uart_init.c has OS_FLAG_SET as undeclared, and similarly, it says the BSP file altera_avalon_uart_read.c has OS_FLAG_WAIT_SET_ANY undeclared. Also, altera_avalon_uart_write.c has OS_FLAG_CONSUME undeclared. How do I get the BSP to build?

I can use UART with HAL rather than FreeRTOS, and it works fine for the Nios V.

(I am using Quartus 23.1 STD.)

  • In the "freertos/drivers/src/":


    • intel_lw_uart_init.c
      • line 228~:

    if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK))

    {

    ALT_FLAG_POST (sp->events,

    ALT_UART_WRITE_RDY,

    ALT_FLAG_SET);

    }


    • intel_lw_uart_read.c
      • line 205~:

    ALT_FLAG_PEND (sp->events,

    ALT_UART_READ_RDY,

    ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME,

    ALT_FLAG_WAIT_MAX_TIMEOUT);


    • intel_lw_uart_write.c
      • line 192~:

    ALT_FLAG_PEND (sp->events,

    ALT_UART_WRITE_RDY,

    ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME,

    ALT_FLAG_WAIT_MAX_TIMEOUT);



22 Replies

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor

    Let me try to reattach:


    • intel_lw_uart_init.c

    • intel_lw_uart_read.c

    • intel_lw_uart_write.c


    Again, for MAX 10, making this changes will increase the size of the .elf, and it would not fit the maximum size for MAX 10's OCRAM due to its size. You may continue to use Altera HAL or in the future consider a bigger FPGA.


  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor

    In the "freertos/drivers/src/":


    • intel_lw_uart_init.c
      • line 228~:

    if (sp->tx_start == ((sp->tx_end + 1) & ALT_AVALON_UART_BUF_MSK))

    {

    ALT_FLAG_POST (sp->events,

    ALT_UART_WRITE_RDY,

    ALT_FLAG_SET);

    }


    • intel_lw_uart_read.c
      • line 205~:

    ALT_FLAG_PEND (sp->events,

    ALT_UART_READ_RDY,

    ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME,

    ALT_FLAG_WAIT_MAX_TIMEOUT);


    • intel_lw_uart_write.c
      • line 192~:

    ALT_FLAG_PEND (sp->events,

    ALT_UART_WRITE_RDY,

    ALT_FLAG_WAIT_SET_ANY_WITH_CONSUME,

    ALT_FLAG_WAIT_MAX_TIMEOUT);



  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hi Andrew,


    We apologize for any inconvenience. Given this, is it okay to proceed with the Altera HAL with your design? Or do you have other FPGA?


    • Andrew099's avatar
      Andrew099
      Icon for New Contributor rankNew Contributor

      We're using external flash to do execute in place, and so it doesn't matter to us that the .elf file won't fit on the Max 10 itself. We're still planning on using the Max 10, and given our current design, we have to use FreeRTOS. We think we know what we need to do going forward. Thank you for your help.

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor

    Hi,


    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.