Honored ContributorWe are interested in using a external flash memory device to store our firmware for our multi-processor design. To boot from this flash device does it need to be CFI compliant or this there other types of FLash devices that we could use (e.g. SPI interface or alternate interface...) ?
Honored ContributorDear Michael,
Thanks for your response. Please could you clarify some more points :- <div class='quotetop'>QUOTE (MSchmitt @ Aug 25 2009, 02:34 PM) <{post_snapback}> (index.php?act=findpost&pid=23590)</div> --- Quote Start --- If your cfi flash is connected via an avalon tri state bridge then this bridge arbitrates the access of different masters. Meaning you can let different masters access this flash as it is a slave to avalon at the same time. Only one of them will gain access, the others must wait. So all nios masters could start to run from this flash at the same time[/b] --- Quote End --- So when would you use a Mutex core ? It sounds like the tri-state bridge does all the arbitration between a shared external source ?! <div class='quotetop'>QUOTE (MSchmitt @ Aug 25 2009, 02:34 PM) <{post_snapback}> (index.php?act=findpost&pid=23590)</div> --- Quote Start --- Also you could add other masters like dma or your custum ip to gain access to a slave. All arbitration is handled via avalon and you setup special behavioral via sopc builder, see altera documentation But you must take care about the following. If one master alternates the cfi you must enshure that no other master accesses this cfi as this would disturb the programming algorithm, so have a look at the datesheet of your cfi[/b] --- Quote End --- Could you please explain the above line a bit more <div class='quotetop'>QUOTE (MSchmitt @ Aug 25 2009, 02:34 PM) <{post_snapback}> (index.php?act=findpost&pid=23590)</div> --- Quote Start --- In your application with external cfi flash as boot medium all nios reset pointers can point to the same slave, even to the same reset adress and start at the same time. In fact the avalon bridge will multilex the access. This is very well documented by altera avalon specification. You must take about caches, but you are aware of that already. It would also be possible to share slaves like sdram between the different nios.[/b] --- Quote End ---Honored Contributorassume nios cpu 0 tries to programm the cfi flash, then no other nios cpu or any other master should access the cfi flash as it disturbs the programming algorithm. have a look at the datasheet of these cfi flash devices. there is a given access order you must use otherwise it could happen that the cfi flash wont accept a programming information due to an out of order access from a different master. in that case the programming cpu won't notice that and you will hardly dig down your false cfi flash programming.
