Honored Contributor
Honored Contributor<div class='quotetop'>QUOTE </div>
--- Quote Start --- You'll probably have to partition your RAM so that 2ndary bootloader and real code have their own isolated sections, with the bootloader section clearly being much smaller.[/b] --- Quote End --- How do I partition the RAM? Specifically, how do I make the linker think that the RAM is smaller than it really is? I am worried about overwriting the heap or stack of the 2ndary boot loader with the real code. How to I limit the amount of RAM left over for the heap and stack? <div class='quotetop'>QUOTE </div> --- Quote Start --- You may even be able to fit your 2ndary bootloader in on-chip RAM, which will make this problem a lot simpler as you wont have to worry about booting code from the EPCS at all since M4K memories in Cyclone parts are initializable with the FGPA configuration stream.[/b] --- Quote End --- This would be ideal, but I don't have any free M4Ks. We have a lot of dual-port memory in our system. The .elf to .srec conversion is what I expected. Thanks. <div class='quotetop'>QUOTE </div> --- Quote Start --- Lastly, once the real code (including all data sections) is in place, you simply have to branch to it's starting address. If the code was built using Nios II IDE, all the system initialization will taken care of including stack pointer, heap, and the like.[/b] --- Quote End --- Won't the IDE generate new .entry and .exceptions sections? Doesn't the .exceptions section have to be at 0x20 (assuming I haven't changed the default in SOPC Builder?) Thanks for your help.
