Forum Discussion
Altera_Forum
Honored Contributor
13 years agoHi,
you have to store the fpga configuration data and the nios firmware in the EPCS. I'm using following script: sof2flash --input="fpga_design.sof" --output="fpga_design.flash" --epcs --verbose elf2flash --input="nios_firmware.elf" --output="pr4_top_fw.flash" --epcs --after="fpga_design.flash" --verbose nios2-flash-programmer --cable='USB-Blaster [USB-0]' --epcs --base=<EPCS Addr> fpga_design.flash nios2-flash-programmer --cable='USB-Blaster [USB-0]' --epcs --base=<EPCS Addr> nios_firmware.flash In my QSYS the reset vector is pointed to EPCS, the exception to onchip RAM because of faster ISRs. Verify in BSP Builder that all other sections are mapped to sdram. Then it should work. Jens