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Honored Contributor
Honored Contributorboot NIOS from EPCS flash and use SDRAM to store instructions and data
Hi! In the qsys I have: 1. Clock Source 2. On-Chip Memory 3. Nios II Processor 4. System ID 5. JTAG UART 6. EPCS Serial Flash Controller 7. PIO 8. SDRAM Controller I want to use...
Altera_ForumHonored Contributor
Honored ContributorHi,
you have to store the fpga configuration data and the nios firmware in the EPCS. I'm using following script: sof2flash --input="fpga_design.sof" --output="fpga_design.flash" --epcs --verbose elf2flash --input="nios_firmware.elf" --output="pr4_top_fw.flash" --epcs --after="fpga_design.flash" --verbose nios2-flash-programmer --cable='USB-Blaster [USB-0]' --epcs --base=<EPCS Addr> fpga_design.flash nios2-flash-programmer --cable='USB-Blaster [USB-0]' --epcs --base=<EPCS Addr> nios_firmware.flash In my QSYS the reset vector is pointed to EPCS, the exception to onchip RAM because of faster ISRs. Verify in BSP Builder that all other sections are mapped to sdram. Then it should work. Jens
